The invention concerns digital filters used in digital signal processing (DSP) applications and, in particular, is directed to a method for optimizing digital filters such as finite impulse response (FIR) filters and convolution filters.
FIR filters and convolution filters are defined by a fixed set of coefficients that are multiplied by input data and accumulated to compute an overall result. For example, a FIR filter can be represented by the following equation:
                              y          ⁡                      (            n            )                          =                              ∑                          i              =              0                        n                    ⁢                                          ⁢                                    c              i                        *                          x              i                                                          (        1        )            where ci represents the filter coefficients. As the number of coefficients increases, the computational resources required to implement the filter correspondingly increase.
Digital filters are often implemented directly in hardware. The multipliers and adders needed to implement digital filters increase the computational complexity of a system and consume valuable chip resources. In most applications it is desirable to minimize the hardware resources required to satisfy a system specification. Accordingly, a continuing need exists to develop techniques for optimizing the structure of digital filters so as to minimize the resources needed to implement the filters.